Job description
The selected candidate will be responsible for implementing high-speed high-volume data generation and handling requirements on FPGA based hardware, including storage in and playback from SSDs/SSRs and high speed serial (SERDES, going to several Gbps) / Parallel (LVDS exceeding a hundred MHz). The subsystems are for use in state-of-the-art spaceborne payloads for high performance
applications in indigenous private sector satellites in India. The work typically may involve, but not necessarily be limited to, the following activities:
Understanding hardware component/environment capabilities, requirements and limitations and evolving firmware architectures and coding for required performance goals.
Be a team contributor, code for parts of a larger functionality and seamless integrate and test the integrated firmware.
Parttake in the full development cycle and not just “design” or verification, and be responsible for subsystem level outcome in an integrated system.
Prepare documents necessary at different stages and be able to interact with QA/QC guidelines and facilitate assurance of code compliance to a given standard.

The knowledge base required in the candidate will in general be a clear understanding of the fundamentals of
Coding for FPGA environment, a significant experience profile of doing this.
Excellent familiarity and skill in VHDL (or Verilog)
Knowledge of the architectures of modern high-density FPGAs and SoC Devices from Xilinx (Now AMD) or Actel (Now Microchip) FPGAs and familiarity with the use of these
Excellent familiarity with the development environments for these devices and the simulation and pre-burn performance validation tools
Very good experience of actually porting developed code into the hardware platforms and test the same for target performance characteristics, and the skill in spotting problems and be able to relate observations in tests back to necessary refinements in code.
Exposure to safe coding practices and high reliability engineering
Specific successful design experience with at least one of the following:
Implementation of high-speed SERDES data links going to several Gbps – and testing for the same
Implementation of SSD interfaces and familiarity with modern SSD interface standards
Implementation of gigabit ethernet solutions in FPGA environments and testing for the same

The successful candidate is likely to have
An electronics degree, masters preferred but not necessary.
A consistent career in FPGA based firmware design and coding (6 to 10 years at least) with exposure to high density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs with many designs turned out successfully.
Good experience in debugging systems, including the ability to probe hardware and make sense of the time domain / frequency domain observations.
A good knowledge of how to estimate rough-order-of-magnitude power consumption figures even before a full design is evolved.

Note: Interviews are likely to be multi-level very detailed. Please who do not check most of the points above may not be suitable at all.